The present invention relates to changing words with uncorrectable errors (UE's) into memory words that can be corrected by the error correcting code protecting the data in the memory.
In copending Bossen et al patent application Ser. No. 362,925, filed Mar. 29, 1982, now U.S. Pat. No. 4,461,001, issued 7/17/84, and entitled "Deterministic Permutation Algorithm", a memory address register accesses a memory word by supplying the same logical address to decoders for all bit positions of the word. However, as a result of modification by logic circuitry, the address actually applied to the decoder of any particular bit position can differ from the logical address supplied by the address register. The logic circuitry is called permutation logic. Because of the permutation logic, a memory word can contain storage cells located at a number of different physical addresses that are not the logical address supplied by the memory register.
In the above mentioned U. S. patent application, memory arrays for each of the bit positions of the codewords of the memory are accessed through a separate chip row decoder so that it is possible to disperse uncorrectable errors (UE's) that result from faulty bits in any combination of bit positions in a codeword by swapping the logical addresses of arrays. While such a memory configuration is desirable from an error correction standpoint it would be more cost effective to have each chip row decoder access arrays in many bit positions in the codeword. For instance, instead of having thirty-nine chip row decoders access a separate row of arrays in a codeword with thirty-nine bit positions three decoders each access thirteen of the thirty-nine bit positions. With this configuration the permutation apparatus of the mentioned Bossen et al patent application would be capable of eliminating UE's that occur as a result of alignment of faults in bit positions accessed through different decoders but incapable of eliminating errors that occur as a result of faults that occur in bit positions accessed through the same decoder.
In copending Bond U.S. application Ser. No. 381,266, filed May 24, 1982, entitled "Fault Alignment Control System and Circuits", now U.S. Pat. No. 4,489,403, this intradecoder fault problem is handled by splitting an n bit decoder for a plurality of bit positions into a single bit decoder and a multibit decoder. Access is then accomplished on two axes of the matrix of arrays where n-1 of the bits access a particular row of arrays with two arrays in each of the plurality of bit positions and selection of one array out of the two in each bit position is then accomplished with the remaining address bit.
Fault dispersion is accomplished in this memory by using two different sets of translation control bits. In addition to row permutation logic described in the Bossen et al application, the Bond U.S. patent application employs an additional single bit translation logic associated with the single bit decoder to displace aligned faults in different arrays for bit positions accessed by the same chip row decoder. This single bit translation logic swaps the logical addresses of the two chips in any bit position accessed by the same row select address. Once the two chips are swapped to eliminate one UE the single translation bit cannot be used again to disperse UE's without first swapping arrays in the other bit positions to eliminate previously dispersed UE's.
In Singh et al U.S. patent application Ser. No. 528,769 filed on even date herewith and entitled "Memory Correction Scheme Using Spare Arrays", a technique and apparatus is described for substitution of a good array for a bad array where the good array can be substituted for an array in any row and column position in a matrix of arrays.